High-speed Ethernet systems often employ multiple link ports that allow multiple transceiver link partners to exchange data traffic. Each link generally includes a physical interface circuit (PHY) that interfaces with a media access controller (MAC). For one IEEE Standard, more specifically IEEE 802.3 Clauses 22 and 45, the data link between each MAC and PHY is realized by a Serializer Deserializer (SERDES) link, such as a Serial Gigabit Media Independent Interface (SGMII). The SGMII employs two differential signal paths to convey transmit and receive data and optionally corresponding clock signals. Control and status updates regarding the PHY are typically managed through a separate serial link known as a Management Data Input/Output (MDIO) interface. MDIO signals are typically routed along a separate multi-drop bus from a Station Management entity (STA) to each PHY.
While the conventional IEEE 802.3 Standard works well for its intended applications, the use of a separate interface to handle MDIO operations generally involves extra pins on each PHY and is often limited in speed. This may be undesirable from circuit pin count, design, and performance perspectives.